4 - 10 Years
Good knowledge on different Memory Architecture and Drawing layouts for schematics created by Design Engineers in 7nm and other FinFET technologies
· Experience on Memory Layout. Like RAM, ROM, SDRAM etc.
· Good knowledge on Memory layout techniques like Area/Speed/Power optimization
· Knowledge on BIT cell, data line & Address line routing concepts
· Effectively communicate with Design Engineers to clarify and interpret the layout requirements based on the schematics
· Prepare layout floor-plan and review it with the Design Engineer
· Create layouts in the Cadence Virtuoso CAD platform as per floor-plan
· Run DRC, LVS and other verifications required by customer to ensure layout meets foundry requirements
· Provide feedback to Design Engineers on any modifications to schematics after layouts are completed
· Support RC-extraction, IR drop and other post-layout analysis of layouts as per Design Engineers requirements
· Layout rework arising from quality issues identified during layout reviews without a material impact to customer’s product schedules.
|Salary||8 Lac To 12 Lac P.A.|
|Industry||IT Hardware / Technical Support / Telecom Engineering|
|Work Experience||4 - 10 Years|
|About Company||HR Consulting|